The semiconductor-on-insulator technology constitutes a new technique for fabricating high-speed MOS and CMOS circuits. According to such a technique, a thin epitaxial layer of semiconductor material, such as silicon, is deposited on an insulator to reduce the capacitive coupling between the semiconductor layer and the underlying insulator and substrate material. Field effect transistors and other devices fabricated within the thin layer of semiconductor material exhibit high-speed switching characteristics.
MOS-type circuits are particularly susceptible to damage by electrostatic discharge. According to current fabrication techniques, the thin gate insulators of MOS and CMOS transistors can be damaged by gate voltages in excess of about seventeen volts. Hence, static discharges by persons or equipment handling such integrated circuits can permanent damage an entire chip. Static discharge destruction of integrated circuits is particularly troublesome, in that electrostatic voltage buildups on a person can reach hundreds to thousands of volts.
While electrostatic discharge (ESD) protection devices have been implemented as ancillary circuits on MOS-type integrated circuit chips, an additional concern arises with semiconductor-on-insulator chips. Traditionally, the energy of an electrostatic discharge was maintained at a safe voltage level by such ancillary protection circuits, and the energy was dissipated in the bulk semiconductor substrate on which the circuits were fabricated. In contrast, with semiconductor-on-insulator SOI) circuits, the thin semiconductor layer has insubstantial bulk to safely, dissipate all the electrostatic energy as thermal energy. Since most electrically insulating materials are poor thermal conductors, substantially all the energy must be dissipated within the thin semiconductor layer which overlies the insulator on SOI chips.
Input protection circuits are well known for use on silicon-on-sapphire (SOS) substrates. The following technical articles are illustrative of the ESD protection circuits adapted for SOI structures: R. K. Pancholy and T. J. Oki, "C-MOS/SOS Gate-Protection Networks", IEEE Trans. on Elec. Dev., Vol. ED-25, pp. 917, 1978; S. H. Cohen and G. K. Caswell, "An Improved Input Protection Circuit for C-MOS/SOS Arrays" ibid, pp. 926; B. T. Ahlport, J. R. Cricchi and D. A. Barth, "C-MOS/SOS LSI Input/Output Protection Networks" ibid, pp. 933; and W. Palumbo and M. P. Dugan, "Design and Characterization of Input Protection Networks for CMOS/SOS Application", EOS/ESD SYMPOSIUM PROCEEDINGS, pp. 182, 1986. Typical of such input protection networks is a gated diode or a p-i-n diode which exhibits a forward threshold of about 0.7 volts and a reverse breakdown voltage of about 14 volts. Thus, the clamping of input gate voltages to less than the requisite 17 volts is achieved. More importantly, the energy developed across such a protection diode when operating at a breakdown voltage of about 14 volts can be substantial. The heat generated by such diodes must be dissipated by the thin semiconducter layer which, if such energy becomes excessive, poses the danger of destruction to the integrated circuit chip.
From the foregoing, it can be seen that a need exists for improved electrostatic discharge protection circuits which can be easily fabricated and which are compatible with other transistors on the chip, as well as provide a lower voltage drop thereacross to thereby reduce the thermal energy dissipation requirements of the thin semiconductor layer of the SOI structure. An associated need exists for an electrostatic discharge protection circuit which can be fabricated according to current silicon processing techniques and equipment.